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Power Management Switch IC Series for PCs and Digital Consumer Product
1ch Small Current Output Power Managment Switch IC
BD6524HFV
No.09029EAT13
Description Power switch for memory card Slot (BD6524HFV) is a high side switch IC having one circuit of N-channel Power MOS FET. The switch realizes 200m (Typ.) ON resistance. Operations from low input voltage (VIN 3.0V) can be made for use for various switch applications. The switch turns on slowly by the built-in charge pump, therefore, it is possible to reduce inrush current at switch on. There is no parasitic diode between the drain and the source, reverse current flow at switch off is prevented. Further, it has a discharge circuit that discharges electric charge from capacitive load at switch off. The BD6524HFV is available in a space-saving HVSOF6 package. Features 1) Low on resistance (200m, Typ.) N-MOS switch built in 2) Maximum output current : 500mA 3) Soft start circuit 4) Under voltage lockout (UVLO) circuit 5) Discharge circuit built in : operations at switch off, UVLO 6) Reverse current flow blocking at switch off Applications Memory card slots of notebook PC, digital still camera, portable music player, compact portable devices such as PDA and so forth Absolute Maximum Ratings Parameter Supply Voltage Control input voltage Switch output voltage Storage temperature Power dissipation
*1 * *
Symbol VIN VEN VOUT TSTG Pd
Rating -0.3 to 6.0 -0.3 to VIN + 0.3 -0.3 to 6.0 -55 to 150 510 *1
Unit V V V mW
Derating : 4.08mW/ for operation above Ta = 25. This product is not designed for protection against radioactive rays. Operation is not guaranteed.
Operation conditions Parameter Supply voltage Operating Temperature Switch current Symbol VIN TOPR IOUT Limit 3.0 to 5.5 -25 to 75 500 Unit V mA
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1/9
2009.05 - Rev.A
BD6524HFV
Electrical characteristics Unless otherwise specified, Ta = 25, VIN = 5V, Limit Parameter Symbol Min. Typ. Operating current IDD 50 Standby current ISTB 0.1 EN input voltage EN input leak current Switch on resistance Switch leak current Switch rise time Switch rise delay time Switch fall time Switch fall delay time UVLO threshold voltage Discharge resistance Discharge current VENH VENL IEN RON ILEAK TON1 TON2 TOFF1 TOFF2 VUVLO RDISC IDISC 0.7 -1 1.9 1.8 0.8 0.01 200 250 0.4 0.5 1 2 2.2 2.1 200 1.8
Technical Note
Max. 75 1 2.5 1 255 335 10 0.8 1.0 2 4 2.5 2.4 350 -
Unit A A V V A m m A ms ms us us V V mA
Condition VEN = 5V, VOUT = Open VEN = 0V, VOUT = Open High level input voltage Low level input voltage
VIN = 5V VIN = 3.3V At switch OFF RL=10. Refer to the timing diagram in Fig. 2. RL=10. Refer to the timing diagram in Fig. 2. RL=10. Refer to the timing diagram in Fig. 2. RL=10. Refer to the timing diagram in Fig. 2. VIN increasing VIN decreasing VEN = 0V, IL = 1mA VEN = 0V,VIN = VOUT = 1.8V
Measurement circuit
VIN VIN EN
VOUT VOUT
RL CL
GND
Fig.1 Measurement circuit Timing diagram
TOFF1 TON1 VOUT 10% 90% 90% 10%
TON2 VEN 50% 50% TOFF2
Fig.2 Timing diagram
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2009.05 - Rev.A
BD6524HFV
Typical characteristics
50 OPERATING CURRENT:IDD[uA] 45
STAND-BY CURRENT:ISTB[uA] 0.10
Technical Note
2.5 EN INPUT VOLTAGE:V ENH [V]
40 35 30 25 20 15 10 5 0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
0.08
2.0
0.06
1.5
0.04
1.0
0.02
0.5
From above :VIN=3.0V,5.0V,5.5V
From above: VIN=5.5V,5.0V,3.0V
0.00 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
0.0 -25 0 25 50 75 AMBIENT TEMPETRATURE:Ta[]
Fig.3 Operating current
2.5
Fig.4 Standby current
350 300 250 200 150 100 50 0
Fig.5 EN threshold voltage (High level input voltage)
0.9 0.8 TURN ON TIME1:TON1[ms] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
From above: VIN=3.0V,4.0V,5.0V,5.5V
EN INPUT VOLTAGE:VENL[V]
2.0
1.5
1.0
0.5
ON RESISTANCE:RON [mO]
From above: VIN=5.5V,5.0V,3.0V
From above: VIN=3.0V,5.0V,5.5V
0.0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
-25
0
25
50
75
-25
0
25
50
75
AMBIENT TEMPERATURE:Ta[]
AMBIENT TEMPERATURE:Ta[]
Fig.6 EN threshold voltage (Low level input voltage)
0.9 0.8
Fig.7 Switch on resistance
3.5 3.0 TURN OFF TIME1:T OFF1[us] 2.5 2.0
From above: VIN=3.0V,4.0V,5.0V,5.5V
Fig.8 Switch rise time
3.5 3.0 TURN OFF TIME2:T OFF2[us] 2.5 2.0 1.5 1.0 0.5 0.0
From above: VIN=3.0V,4.0V,5.0V,5.5V
TURN ON TIME2:T ON2[ms]
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
1.5 1.0 0.5 0.0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
From above: VIN=3.0V,5.0V,5.5V
-25
0
25
50
75
AMBIENT TEMPERATURE:Ta[]
Fig.9 Switch rise delay time
Fig.10 Switch fall time
Fig.11 Switch fall delay time
3.0 2.5 2.0 1.5 1.0 0.5 0.0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
DISCHARGE RESI STANCE:RDISC [ ]
250
UVLO THRESHOLD:VUVLO[V]
VIN increasing VIN decreasing
200
150
100
50
From above: VIN=3.0V,4.0V,5.0V,5.5V
0 -25 0 25 50 75 AMBIENT TEMPERATURE:Ta[]
Fig.12 UVLO threshold voltage
Fig.13 Discharge resistance
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3/9
2009.05 - Rev.A
BD6524HFV
Technical Note
50 45 OPERATING CURRENT:I D[uA] D
EN INPUT VOLTAGE:VEN[V]
2.5
350 300
35 30 25 20 15 10 5 0 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE:VIN[V]
VENH
ON RESISTANCE:RON[m]
5 5.5
40
2.0
250 200 150 100 50 0
1.5
VENL
1.0
0.5
0.0 3 3.5 4 4.5 INPUT VOLTAGE:VIN[V]
3.0
3.5
4.0
4.5
5.0
5.5
Fig.14 Operating current
0.9 0.8
Fig.15 EN threshold voltage
3.5 3.0
TURN OFF TIME:T OFF[us]
DISCHARGE RESISTANCE:RDISC[] 250
Fig.16 Switch on resistance
INPUT VOLTAGE:VIN[V]
TURN ON TIME:T ON[ms]
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3 4 5 5.5 INPUT VOLTAGE:VIN[V]
200
2.5 2.0 1.5 1.0 TOFF1 0.5 0.0 3 4 5 5.5 INPUT VOLTAGE:VIN[V] TOFF2
TON2
150
TON1
100
50
0 3 3.5 4 4.5 5 5.5 INPUT VOLTAGE:VIN[V]
Fig.17 Switch rise time
Fig.18 Switch fall time
Fig.19 Discharge resistance
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2009.05 - Rev.A
BD6524HFV
Waveform data
Technical Note
RL=10, CL=10uF EN (1V/div) VIN = 5V EN (1V/div)
RL=10, CL=10uF EN (1V/div) VIN = 5V
RL=10, CL=10uF VIN = 3V
0.42ms VOUT (1V/div) VOUT (1V/div)
1.05ms VOUT (1V/div)
0.74ms
Time (200us/div)
Time (500us/div)
Time (200us/div)
Fig.20 Switch rise time
Fig.21 Switch fall time
Fig.22 Switch rise time
EN (5V/div)
EN (1V/div)
RL=10, CL=10uF VIN = 3V
VIN = 5V CL = 10uF CL = 4.7uF
EN (5V/div)
VIN = 3V
1.10ms Irush (50mA/div) Irush (50mA/div) VOUT (1V/div) CL = 1uF
CL = 10uF CL = 4.7uF CL = 1uF
Time (500us/div)
Time (100us/div)
Time (100us/div)
Fig.23 Switch fall time
Fig.24 Inrush current
Fig.25 Inrush current
VIN (1V/div)
VOUT (1V/div)
50ms Time (20ms/div)
VOUT (1V/div)
VIN (1V/div)
5ms Time (20ms/div)
Fig.26 UVLO CL = 10uF
Fig.27 UVLO CL = 1uF
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5/9
2009.05 - Rev.A
BD6524HFV
Block diagram
Technical Note
GND
4 charge pump
VIN 1,2
VIN 1 VIN 2 EN 3
6 VOUT 5 VOUT 4 GND
EN
3
control logic
VOUT 5,6
Fig.28 Pin configuration
Fig.29 Block diagram
Pin description Pin No. 1 2 3 4 5 6
Symbol VIN EN GND VOUT
Pin Function Switch input pin. At use, connect each pin outside. Switch control input pin (hysteresis input) Switch ON at High. Ground Switch output pin At use, connect each pin outside.
I/O circuit
VIN
VIN
EN
VOUT
Fig.30 I/O circuit
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6/9
2009.05 - Rev.A
BD6524HFV
Technical Note
Functional description 1. Input / output VIN pin and VOUT pin are connected to the drain and the source of N-MOS switch respectively. And the VIN pin is used also as power source input to internal control circuit. When EN input is set to High level and the switch is turned on, VIN pin and VOUT pin are connected by a 200m switch. In a normal condition, current flows from VIN to VOUT. If voltage of VOUT is higher than VIN, current flows from VOUT to VIN, since the switch is bidirectional. There is not a parasitic diode between the drain and the source, it is possible to prevent current from flowing reversely from VOUT pin to VIN pin when the switch is disabled. 2. Discharge circuit When the switch between the VIN and the VOUT is OFF, the 200(Typ.) discharge switch between VOUT and GND turns on. By turning on this switch, electric charge at capacitive load is discharged. 3. Under voltage lockout (UVLO) The UVLO circuit monitors the voltage of the VIN pin, when the EN input is active. UVLO circuit prevents the switch from turning on until the VIN exceeds 2.2V(Typ.). If the VIN drops below 2.1V(Typ.) while the switch turns on, then UVLO shuts off the switch. While the switch between the VIN pin and VOUT pin is OFF owing to UVLO operations, the switch of the discharge circuit turns on. However, when the voltage of VIN declines extremely, then the VOUT pin becomes Hi-Z.
VIN VEN VOUT
Discharge circuit
2.1V(Typ.)
2.2V(Typ.)
ON
OFF
ON
OFF
ON
OFF
Fig.31 Operation timing
Typical application circuit
VIN VIN 0.11uF EN EN
VOUT VOUT GND LOAD
Fig.32 Typical application circuit
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7/9
2009.05 - Rev.A
BD6524HFV
Technical Note
Notes for use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Thermal design Perform thermal design in which there are adequate margins by taking into account the power dissipation (Pd) in actual states of use.
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8/9
2009.05 - Rev.A
BD6524HFV
Ordering part number
Technical Note
B
D
6
Part No. 6524
5
2
4
H
F
V
-
T
R
Part No.
Package HFV: HVSOF6
Packaging and forming specification TR: Embossed tape and reel (HVSOF6)
HVSOF6

1.60.1 (MAX 1.8 include BURR)
2.60.1 (MAX 2.8 include BURR) (1.5)
Tape Quantity
(0.45)
Embossed carrier tape 3000pcs TR
The direction is the 1pin of product is at the upper right when you hold
654
3.00.1
Direction of feed
(1.2) (1.4)
123
( reel on the left hand and you pull out the tape on the right hand
1pin
)
(0.15)
0.1450.05 S 0.1 S 0.220.05 0.5
0.75Max.
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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2009.05 - Rev.A
Notice
Notes
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